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A comprehensive reference on design-for-testability (DFT) methods for Very Large Scale Integration (VLSI) circuits. The book covers fundamental principles and architectures for testing, including logic and fault simulation, test generation, built‑in self‑test (BIST), test compression, memory testing and repair, boundary‑scan, mixed‑signal testing, and emerging nanometer‑age test technologies. It is designed for engineers, designers, and researchers working on integrated circuit testing and quality assurance

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245: $a: VLSI Test Principles and Architectures
245: $b:
082: $a:
100: $a: Laung‑Terng Wang & Cheng‑Wen Wu & Xiaoqing Wen
650: $a: Computer Engineering
250: $a:
440: $v:
250: $b: Elsevier Churchill Livingstone
250: $c: 2006
020: $a: 978‑0123705976
300: $a: 808